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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADS58C48IPFPR bảng dữ liệu(PDF) 32 Page - Texas Instruments |
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ADS58C48IPFPR bảng dữ liệu(HTML) 32 Page - Texas Instruments |
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32 / 70 page  −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) Each Tone at −7dBFS Fin1 = 185MHz Fin2 = 190MHz Two−Tone IMD = 83.3dBFS SFDR = 89.1dBFS −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) Each Tone at −36dBFS Fin1 = 185MHz Fin2 = 190MHz Two−Tone IMD = 97.4dBFS SFDR = 99.8dBFS −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 70 80 90 Frequency (MHz) Ain =−36dBFS,Fin =140MHz, Fs = 185 MSPS Over 60MHz BW,17M to 77M SNR = 75.1 dBFS SINAD = 75.05 dBFS SFDR = 61 dBc SNR BOOST Filter # 40 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 0 10 20 30 40 50 60 70 80 90 Frequency (MHz) Ain = −2dBFS,Fin = 140MHz, Fs = 185 MSPS Over 60MHz BW,17M to 77M SNR = 72.3 dBFS SINAD = 72.1 dBFS SFDR = 83 dBc SNR BOOST Filter # 40 ADS58C48 SLAS689 – MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain, DDR LVDS output interface, 32k point FFT (unless otherwise noted) FFT FOR TWO −TONE INPUT SIGNAL FFT FOR TWO −TONE INPUT SIGNAL Figure 12. Figure 13. FFT WITH SNRBoost 3G ENABLED, 60-MHz BANDWIDTH FFT WITH SNRBoost 3G ENABLED, 60-MHz BANDWIDTH Figure 14. Figure 15. 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :ADS58C48 |
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