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FlexBus Memory Map

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

115

Because of the odd size of the SRAM (20KB) and the mirroring on a 32KB boundary, there will be a “hole”

in the upper 16KB of each mirrored 32KB where no reads or writes are allowed. Any write or read to this

hole will produce a bus abort. Please refer to Section 19.1.6.2, “SRAM Address Mirroring” for more

details on the mirroring in the SRAM controller.

The default base address for the SRAM is $4000 0000 and is not selectable during reset, but is software

selectable after reset.

9.11

FlexBus Memory Map

Like the Peripheral Bus modules, the FlexBus resides on a slave port of the AXBS, and therefore has a

movable base address on a 512MByte boundary. In addition, the FlexBus has 3 chip-selects, where each

chip select can select from 64KBytes to 512MBytes, and may overlap.

The default base address for the FlexBus depends on the chip mode selected (See Figure 9-1) and is

software selectable after reset. Note that in some modes, the Flexbus is not available in the memory map

(for security reasons).

9.12

Flash Main Array Memory Map

The Flash main array is relocatable on any 512 MByte boundary, including $0000 0000 (via the AAMR

Chip and PBL Mode. The base address is software selectable in any chip mode. Note that in some modes,

the Flash Main Array is not available in the memory map (for security reasons).

$1FFF 0000

$1FFF 7FFF

SRAM

$1FFF 8000

$1FFF FFFF

SRAM

Table 9-13. FlexBus Memory Map

Address Offset

Function

$0000 0000

$1FFF FFFF

FlexBus

Table 9-12. SRAM Memory Map (Continued)

Address Offset

Function

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