MAC7200 datasheet(126/976 Pages) FREESCALE

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Detailed Signal Descriptions

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

pin. It is multiplexed with the Transfer Acknowledge input for devices connected to the external bus. It

can be configured to wake the system out of low-power mode (DOZE) when an external signal is applied

using the interrupt functionality.

4.3.43

PD[15] / CS0 — Port D I/O Pin and External Bus Control

PD[15] is a configurable general purpose input or output pin. The pin can be configured to provide either

high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the

pin. It is multiplexed with the Chip Select 0 output for devices connected to the external bus. It can be

configured to wake the system out of low-power mode (DOZE) when an external signal is applied using

the interrupt functionality.

4.3.44

PD[15] / R/W — Port D I/O Pin and External Bus Control

PD[15] is a configurable general purpose input or output pin. The pin can be configured to provide either

high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the

pin. It is multiplexed with the Read/Write output for devices connected to the external bus. It can be

configured to wake the system out of low-power mode (DOZE) when an external signal is applied using

the interrupt functionality.

4.3.45

PE[0:15] / AN_A[00:15]— Port E I/O Pins and ATD_A

PE[0] to PE[15] are configurable general purpose input pins (Note that general purpose output

functionality is not available). They can be configured to enable or disable either a pull-up or pull-down

resistor on the pins. The pins are multiplexed with the analog inputs AN_A[00:15] for the analog to digital

converter (ATD_A), and may be used either as an Analog Channel or an external ATD trigger. Each pin

can be independently configured to wake the system out of low-power mode (DOZE) when an external

signal is applied using the interrupt functionality.

4.3.46

PF[0] / EMIOS[0] / NEXPS — Port F I/O Pins, eMIOS Channels and

Nexus Port Selection

PF[0] is a configurable general purpose input or output pin. It can be independently configured to provide

either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on

the pin. The pin is multiplexed with the eMIOS channels for the capturing of timed events or the output of

time based signals. At Reset the value of the pin is used to determine the position of the Nexus Port (when

enabled). NEXPS cleared low selects the Primary Nexus Port (PA[0:6]), NEXPS set high selects the

Secondary Nexus Port (PE[0:6]). The pin can be independently configured to wake the system out of

low-power mode (DOZE) when an external signal is applied using the interrupt functionality.

4.3.47

PF[1] / EMIOS[1] / NEXPR — Port F I/O Pins, eMIOS Channels and

Nexus Present Selection

PF[1] is a configurable general purpose input or output pin. It can be independently configured to provide

either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on

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