MAC7200 datasheet(313/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

235

12.2.6

Initialization/Application Information

12.2.6.1

DMA Initialization

A typical initialization of the DMA would be:

1. write the DMACR register if a configuration other than the default is desired,

2. write the channel priority levels into the DCHPRIn registers if a configuration other than the

default is desired,

3. enable error interrupts in the DMAEEI registers if so desired,

4. write the 32 byte TCD for each channel that may request service,

5. enable any hardware service requests via the DMAERQ register,

6. request channel service by either software (setting the TCD.start bit) or by hardware (slave device

asserting its ipd_req signal).

Once any channel requests service, a channel is selected for execution based on the arbitration and priority

levels written into the programmer's model. The dma_engine will read the entire TCD for the selected

channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the

AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source

address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until

the specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the

dma_engine's local TCD.saddr, TCD.daddr, and TCD.citer are written back to the main TCD memory and

any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post

processing is executed, i.e. interrupts, major loop channel linking, and scatter/gather operations, if enabled.

12.2.6.2

DMA Programming Errors

The DMA performs various tests on the Transfer Control Descriptor to verify consitency in the descriptor

data. Most programming errors are reported on a per channel basis with the exception of Channel Priority

Error, CPE in the DMAES register respectively.

For all error types other than Channel Priority Errors, the channel number causing the error is recorded in

the DMAES register. If the error source is not removed before the next activation of the problem channel,

the error will be detected and recorded again.

In general, if priority levels are not unique, the highest channel priority that has an active request will be

selected, but the lowest numbered channel with that priority will be selected by arbitration and executed

by the dma_engine. The hardware service request handshake signals, error interrupts and error reporting

will be associated with the selected channel.

12.2.6.3

DMA Arbitration Mode Considerations

12.2.6.3.1

Fixed Channel Arbitration

In this mode, the channel service request from the highest priority channel will be selected to execute.

Preemption is available in this scenario only.

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