MAC7200 datasheet(310/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

232

Freescale Semiconductor

12.2.5

DMA Performance

This section addresses the performance of the DMA module, focusing on two separate metrics. In the

traditional data movement context, performance is best expressed as the peak data transfer rates achieved

using the DMA. In most implementations, this transfer rate is limited by the speed of the source and

destination address spaces. In a second context where device-paced movement of single data values

to/from peripherals is dominant, a measure of the requests which can be serviced in a fixed time is a more

interesting metric. In this environment, the speed of the source and destination address spaces remains

important, but the microarchitecture of the DMA also factors significantly into the resulting metric.

The peak transfer rates for several different source and destination transfers are shown in Figure 12-29.

The following assumptions apply to Figure 12-29 and Figure 12-30:

•

Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data

phase

•

All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the

system bus data phase

•

All IPS accesses are 32-bits in size

Table 12-29 presents a peak transfer rate comparison, measured in MBytes per sec.

int_half

Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt

request by setting the appropriate bit in the DMAINT register when the current major iteration count reaches

the halfway point. Specifically, the comparison performed by the dma_engine is (citer == (biter >> 1)). This

halfway point interrupt request is provided to support double-buffered schemes or other types of data

movement where the processor needs an early indication of the transfer’s progress. The halfway complete

interrupt is disabled when biter values are less than two.

0 The half-point interrupt is disabled.

1 The half-point interrupt is enabled.

int_maj

Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt

request by setting the appropriate bit in the DMAINT register when the current major iteration count reaches

zero.

0 The end-of-major loop interrupt is disabled.

1 The end-of-major loop interrupt is enabled.

start

Channel start. If this flag is set, the channel is requesting service. The DMA hardware automatically clears

this flag after the channel begins execution.

0 The channel is not explicitly started.

1 The channel is explicitly started via a software initiated service request.

Table 12-29. DMA Peak Transfer Rates [MBytes/sec]

Platform Speed,

Width

Platform SRAM-to-

Platform SRAM

32b IPS-to-

Platform SRAM

Platform SRAM-to-

32b IPS

66.7 MHz, 32b

133.3

66.7

53.3

Table 12-28. TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions (Continued)

Field

Description

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