MAC7200 datasheet(246/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

168

Freescale Semiconductor

•

Messaging for taken direct branches includes how many sequential instructions were executed

since the last taken branch or exception. Direct (or indirect) branches not taken are counted as

sequential instructions.

•

Messaging for taken indirect branches and exceptions includes how many sequential instructions

were executed since the last taken branch or exception and the unique portion of the branch target

address or exception vector address.

Branch History Messaging (ARM and Thumb modes) facilitates program trace by providing the following

information.

•

Messaging for taken indirect branches and exceptions includes how many sequential instructions

were executed since the last predicate instruction, exception, or taken indirect branch, the unique

portion of the branch target address or exception vector address, as well as a branch/predicate

instruction history field. Each bit in the history field represents a direct branch or predicated

instruction where a value of one (1) indicates taken, and a value of zero (0) indicates not taken.

11.11.2.1.1

ARM7 Indirect Branch Message Instructions

The table below shows the types of instructions and events which cause Indirect Branch Messages or

Branch History Messages to be encoded.

NOTE

Instructions with the Program Counter (PC) as the destination register (R15)

that are interrupted may or may not cause a BTM to be queued depending

on which stage of the pipe the instruction has reached when the interrupt

occurs.

11.11.2.1.2

ARM7 Direct Branch Message Instructions

The table below shows the types of instructions that will cause Direct Branch Messages or will toggle a

bit in the instruction history buffer to be messaged out in a Resource Full Message or Branch History

Message.

Table 11-37. Indirect Branch / Branch History Message Instructions

Source of Indirect Branch Message

Instructions (ARM mode)

Instr. (Thumb mode)

Taken Register / PC Indirect Branch instruction

Sequential instruction w/ PC as destination reg.

any that write to R15 (PC)

Interrupt / exception

swi, undefined instructions

undefined instructions

Return from interrupt / exception

movs, subs, ldm(3)

N/A

Table 11-38. Direct Branch Message Instructions

Source of Direct Branch Message Instructions (ARM mode)

Instr. (Thumb mode)

Taken Direct Branch instruction

b, bl

b(1), b(2), bl

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