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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

127

Chapter 10

ARM7TDMI-S Core

10.1

Introduction

The MAC7200 family is implemented with a licensed ARM7 CPU. This is a 32-bit RISC core with a three

stage pipeline offering high instruction throughput. The core used across the family is the ARM7TDMI-S

which supports both a 32-bit instruction set and a 16-bit instruction set (THUMB) to assist with code

density. No architectural modifications have been made to this core during implementation, enabling the

MAC7200 family to remain compliant to the ARM ISA V4T and existing tool chains. The core has been

configured to support Big Endian memory systems.

For detailed information about the ARM core please consult the following documents:

•

ARM Architecture Reference Manual (Second Edition)

•

ARM7TDMI-S (Rev 4) Technical Reference Manual (Issue A)

10.2

ARM7 Features

•

32-bit ARM7 TDMI-S RISC Core

— Up to 70MHz operating frequency

— Efficient code density through 16-bit instructions (THUMB).

— Alternate general purpose registers.

— Byte (8-bit), Halfword (16-bit), Word (32-bit) data types supported.

— Cores and Memory connected using high performance AMBA AHB bus.

— Integrated E-ICE module for debug

•

Version rev4p3.04

10.3

ARM7 Implementation

The MAC72xx devices use the latest version of the ARM7TDMI-S core available. For the MAC72x2

xM84A masksets and MAC72x1 0M19G maskset, revision rev4p3.04 is used.

Thumb architecture extension

Debug extensions

Enhanced multiplier (32x8) with 64-bit result support

EmbeddedICE Macrocell extension

Fully Synthesizable

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