68HC705SB7 datasheet(89/170 Pages) FREESCALE

89 / 170 page

August 27, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05SB7

SM-BUS

MOTOROLA

REV 2.1

12-11

12.6

PROGRAMMING CONSIDERATIONS

12.6.1 Initialization

Update Frequency Divider Register (FDR) to select a SCL frequency.

Update SM-Bus Address Register (SMADR) to deﬁne its own slave

address.

Set SMEN bit of SM-Bus Control Register (SMCR) to enable the SM-

Bus interface system.

Modify the bits of SM-Bus Control Register (SMCR) to select Master/

Slave mode, Transmit/Receive mode, interrupt enable or not.

12.6.2 Generation of a START Signal and the First Byte of Data Transfer

After completion of the initialization procedure, serial data can be transmitted by

selecting the “master transmitter” mode. If the device is connected to a multi-mas-

ter bus system, the state of the SM-Bus busy bit (SMBB) must be tested to check

whether the serial bus is free. If the bus is free (SMBB = 0), the start condition and

the ﬁrst byte (the slave address) can be sent. An example of a program which

generates the START signal and transmits the ﬁrst byte of data (slave address) is

shown below:

SEI

; DISABLE INTERRUPT

CHFALG

BRSET

5,SMSR,CHFLAG

; CHECK THE SMBB BIT OF THE

; STATUS REGISTER. IF IT IS

; SET, WAIT UNTIL IT IS CLEAR

TXSTART

BSET

4,SMCR

; SET TRANSMIT MODE

BSET

5,SMCR

; SET MASTER MODE

; i.e. GENERATE START CONDITION

LDA

#CALLING

; GET THE CALLING ADDRESS

STA

SMDR

; TRANSMIT THE CALLING

; ADDRESS

CLI

; ENABLE INTERRUPT

12.6.3 Software Responses after Transmission or Reception of a Byte

Transmission or reception of a byte will set the data transferring bit (SMCF) to 1,

which indicates one byte communication is ﬁnished. Also, the SM-Bus interrupt bit

(SMIF) is set to generate an SM-Bus interrupt if the interrupt function is enable

during initialization. Software must clear the SMIF bit in the interrupt routine ﬁrst.

The SMCF bit will be cleared by reading from the SM-Bus DATA I/O Register

(SMDR) in receive mode or writing to SMDR in transmit mode. Software may

serve the SM-Bus I/O in the main program by monitoring the SMIF bit if the inter-

rupt function is disabled. The following is an example of a software response by a

“master transmitter” in the interrupt routine (see Figure 12-5).

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