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68HC705SB7 bảng dữ liệu(PDF) 87 Page - Freescale Semiconductor, Inc

tên linh kiện 68HC705SB7
Giải thích chi tiết về linh kiện  SPECIFICATION (General Release)
PDF  170 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

68HC705SB7 bảng dữ liệu(HTML) 87 Page - Freescale Semiconductor, Inc

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August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
SM-BUS
MOTOROLA
REV 2.1
12-9
SRW — Slave Read/Write Select
When SMAAS is set, the R/W command bit of the calling address sent from
master is latched into the R/W command bit (SRW). By checking this bit, the
CPU can select slave transmit/receive mode according to the command of
master.
1 =
Read from slave, from calling master.
0 =
Write to slave from calling master.
SMIF — SM-Bus Interrupt Flag
1 =
An SM-Bus interrupt has occurred.
0 =
An SM-Bus interrupt has not occurred.
This bit is set when one of the following events occur:
– Transmission (either transmit or receive mode) of one byte
completed. The bit is set at the falling edge of the 9th clock.
– Receive a calling address which matches its own specific address in
slave receive mode.
– Arbitration lost.
RXAK — Receive Acknowledge
When this bit is “0”, it indicates an acknowledge signal has been received after
the completion of 8 bits data transmission on the bus. If RXAK is “1”, it means
no acknowledge signal is detected at the 9th clock. This bit is set upon reset.
1 =
No acknowledgment signal detected.
0 =
Acknowledgment signal detected after 8 bits data transmitted.



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