68HC705SB7 datasheet(67/170 Pages) FREESCALE

67 / 170 page

August 27, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05SB7

16-BIT TIMER

MOTOROLA

REV 2.1

10-5

NOTE

To prevent interrupts from occurring between readings of the ACRH and ACRL,

set the I bit in the condition code register (CCR) before reading ACRH and clear

the I bit after reading ACRL.

10.3

INPUT CAPTURE REGISTERS

Figure 10-6. Timer Input Capture Block Diagram

The input capture function is a means to record the time at which an event occurs.

The source of the event can be selected from the following:

•

External input via the PB1 pin

•

CPF ﬂag from the voltage comparator in the analog subsystem

•

SCL signal from the SMBUS

The input capture source is selected by the TCSEL and ICEN bits.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MCR

TSEN

LVRON

SCLK

CSSEL

TCSEL

ESVEN

SMINLEV

$000B

COPON

reset:

01000000

Figure 10-7. Miscellaneous Control Register (MCR)

ICRH ($0014)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

INPUT CAPTURE (ICF)

RESET

CLOCK

INTERRUPT

ICRL ($0015)

TIMER STATUS REG.

$0012

$0013

INTERNAL

DATA

READ

ICRH

READ

ICRL

LATCH

BUS

EDGE

SELECT

& DETECT

LOGIC

PB1

TCAP

INPUT

SELECT

MUX

CPF

FLAG

ICEN

(bit 4 of $1D)

BIT

INTERNAL

DATA

BUS

TCSEL

(bit 2 of $0B)

SCL

SMBUS

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