P89LPC915FDH datasheet(50/75 Pages) NXP

50 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

50 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.24 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler is either the PCLK or the

nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a

power-on reset. When the watchdog feature is disabled, it can be used as an interval timer

and may generate an interrupt. Figure 21 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog

clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a

time-out period that ranges from a few

µs to a few seconds. Please refer to the

P89LPC915/916/917

User’s Manual for more details.

8.25 Additional features

8.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

8.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 21. Watchdog timer in Watchdog mode (WDTE = 1)

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aaa905

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

PCLK

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

reset(1)

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