P89LPC915FDH datasheet(33/75 Pages) NXP

33 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

33 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.9 Low power select

The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the

power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.10 Memory organization

The various P89LPC915/916/917 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC915/916/917 devices have 2 kB of on-chip Code

memory.

8.11 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 10.

8.12 Interrupts

The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources.

The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0 and

1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout

detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, and ADC completion.

The P89LPC916 supports 14 interrupt sources: external interrupts 0 and 1, timers 0 and

1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion.

Table 10.

On-chip data memory usages

Type

Data RAM

Size (bytes)

DATA

Memory that can be addressed directly and indirectly

128

IDATA

Memory that can be addressed indirectly

256

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