P89LPC915FDH datasheet(42/75 Pages) NXP

42 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

42 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.19.5 Baud rate generator and selection

Each enhanced UART has an independent Baud Rate Generator. The baud rate is

determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which

together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1

but is much more accurate. If the baud rate generator is used, Timer 1 can be used for

other timing functions.

The UART can use either Timer 1 or its baud rate generator output (see Figure 13). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses OSCCLK.

8.19.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’,

SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON [7:6]) are set up when

SMOD0 is ‘0’.

8.19.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

8.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated

when the double buffer is ready to receive new data.

Fig 13. Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

002aaa897

÷2

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