P89LPC915FDH datasheet(34/75 Pages) NXP

34 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

34 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

8.12.1 External interrupt inputs

The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has

one external interrupt input. These external interrupt inputs are identical to those present

on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt

function.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 8.15 “Power reduction modes” for details.

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