AD9148BBCZ datasheet(29/73 Pages) AD

29 / 73 page

Preliminary Technical Data

AD9148

Rev. PrA | Page 29 of 73

Addr

(Hex)

Bit

Name

Function

Default

Sync Control 1

5:0

Sync phase request

Offset of internal divided by 64 clock phase after sync.

000000

000000 = 0 DAC clocks.

…

111111 = 63 DAC clocks.

Sync Status 0

Sync Lost

Synchronization lost.

Read-

only

Sync locked

Synchronization found.

Read-

only

Data Receiver Control

One DCI

0 = two DCIs used, DCIA_x and DCIB_x.

1 = one DCI used, DCIA_x.

Data Receiver Status

LVDS receiver

frame high

Frame input LVDS level > 1.7 V.

Read-

only

LVDS receiver

frame low

Frame input LVDS level < 0.7 V.

Read-

only

LVDS receiver

DCI high

DCI input LVDS level > 1.7 V.

Read-

only

LVDS receiver

DCI low

DCI input LVDS level < 0.7 V.

Read-

only

LVDS receiver

Port B high

Port B input LVDS level > 1.7 V.

Read-

only

LVDS receiver

Port B low

Port B input LVDS level < 0.7 V.

Read-

only

LVDS receiver

Port A high

Port A input LVDS level > 1.7 V.

Read-

only

LVDS receiver

Port A low

Port A input LVDS level < 0.7 V.

Read-

only

FIFO status/

Control Port A

FIFO Warning 1

FIFO read and write pointers within ±1.

Read-

only

FIFO Warning 2

FIFO read and write pointers within ±2

Read-

only

FIFO reset aligned

FIFO read and write pointers aligned after chip reset.

Read-

only

FIFO SPI align

acknowledge

FIFO read and write pointers aligned after SPI driven

FIFO reset.

Read-

only

FIFO SPI align

requesting

Request FIFO read and write pointers alignment via SPI.

2:0

FIFO phase offset

FIFO read and write pointer phase offset from optimal

phase following FIFO reset.

000

000 = 0 offset from optimal phase.

…

111 = 7 offset from optimal phase.

The optimal value is 0.

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