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AD9148BBCZ bảng dữ liệu(PDF) 25 Page - Analog Devices |
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AD9148BBCZ bảng dữ liệu(HTML) 25 Page - Analog Devices |
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25 / 73 page ![]() Preliminary Technical Data AD9148 Rev. PrA | Page 25 of 73 Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x54 FTW (LSB) FTW[7:0] 0x00 0x55 FTW FTW [15:8] 0x00 0x56 FTW FTW[23:16] 0x00 0x57 FTW (MSB) FTW[31:24] 0x00 0x58 Phase offset (MSB) NCO Phase Offset[15:8] 0x00 0x59 Phase offset (LSB) NCO Phase Offset[7:0] 0x00 0x5A DDS/mod control Bypass DDS/MOD Frame NCO reset ack Frame NCO reset request FTW update ack FTW update request Sideband select 0x80 0x5C Die Temp Control 0 Latch temp data Temp Sensor power down 0x01 0x5D Die Temp Control 1 0 0 0 0 1 0 1 0 0x20 0x5E Die temp LSB Die Temp[7:0] 0x5F Die temp MSB Die Temp[15:8] 0x72 DCI delay DCI Delay[1:0] 0x00 0x79 PLL Ctrl (Test) 1 1 1 1 1 1 1 1 0x40 1 Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 1 (I) and DAC 2 (Q) data paths with DAC SPI select = 0 (Register 0x00[4]). Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 3 (I) and DAC 4 (Q) data paths with DAC SPI select = 1 (Register 0x00[4]). SPI REGISTER DESCRIPTIONS Table 13. Register Descriptions Register Name Addr (Hex) Bit Name Function Default Comm 00 7 SDIO SDIO operation. 0 0 = SDIO operates as an input only. 1 = SDIO operates as bidirectional input/output. 6 LSB/MSB first SPI communication LSB first (default is MSB first). 0 0 = MSB first. 1 = LSB first. 5 Software Reset Software reset. 0 Reset is asserted when this bit transitions from 0 to 1. 4 DAC SPI select Selects which DAC data path Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure. 0 0 = DAC 1 (I path) and DAC 2 (Q path) are configured. 0 1 = DAC 3 (I path) and DAC 4 (Q path) are configured. Power Control 01 7 Power-Down DAC Set 1 Power down DAC 1 and power down DAC 2. 0 6 Power-Down DAC Set 2 Power-down DAC 3 and power down DAC 4. 0 5 Power-down data receiver Power down the input data receiver. 0 |
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