AD9148BBCZ datasheet(40/73 Pages) AD

40 / 73 page

AD9148

Preliminary Technical Data

Rev. PrA | Page 40 of 73

BYTE MODE

In byte mode, a FRAME signal must be provided along with the

DCI signal and the data. The most significant byte of the data

should correspond with DCI being high, and the least significant

byte of the data should correspond with DCI being low. The

FRAME signal indicates to which DAC the data is intended.

When FRAME is high, data on the top half of the port (A[15:8])

is sent to DAC 1 and data on the bottom half of the port (A[7:0]) is

sent to DAC 3. When the FRAME is low, data on the top half of

the port is sent to DAC 2 and data on the bottom half of the

port is sent to DAC 4. This pattern continuously repeats as

shown in Figure 48.

FRAMEA

A[15:8]

DAC1H

DAC1L

DAC2H

DAC2L DAC1H

DAC1L

DAC2H

DAC2L

A[7:0]

DAC3H

DAC3L

DAC4H

DAC4L DAC3H

DAC3L

DAC4H

DAC4L

DCIA

Figure 48. Timing Diagram for Byte Mode

The AD9148 also includes a byte swap feature. By default, the

bytes should be formatted as MSB sent to Bit 15 on Bus 1 and

Bit 7 on Bus 2. When byte swap is enabled (Register 0x03[2]),

MSB should be sent to Bit 8 on Bus 1 and Bit 0 on Bus 2. This is

described in Table 14.

Table 14. Byte Swap Formatting

Byte Swap

Byte

A[15:8]

A[7:0]

MSB

Data Set 1[15:8]

Data Set 2[15:8]

LSB

Data Set 1[7:0]

Data Set 2[7:0]

MSB

Data Set 1[8:15]

Data Set 2[8:15]

LSB

Data Set 1[0:7]

Data Set 2[0:7]

DATA INTERFACE OPTIONS

To enable optimization of the data interface, some additional

options have been provided in the following registers:

•

Data format (Register 0x03)

•

Data receiver control (Register 0x14)

•

Data receiver status (Register 0x15)

Depending on the data rate and DCI vs. data skew, the internal

DCI can be inverted to make the valid data timing window.

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