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AD9148BBCZ bảng dữ liệu(PDF) 55 Page - Analog Devices

tên linh kiện AD9148BBCZ
Giải thích chi tiết về linh kiện  Quad 16-Bit,1 GSPS, TxDAC Digital-to-Analog Converter
PDF  73 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD9148BBCZ bảng dữ liệu(HTML) 55 Page - Analog Devices

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Preliminary Technical Data
AD9148
Rev. PrA | Page 55 of 73
The NCO operating frequency, fNCO, is at the DAC rate. The
frequency of the complex carrier signal can be set from dc up to
fDAC/2. The frequency tuning word (FTW) is calculated as
32
2
×
=
DAC
CENTER
f
f
FTW
The generated quadrature carrier signal is mixed with the I and Q
data. The quadrature products are then summed into the I and
Q data paths, as shown in Figure 70.
When using the fine modulator, the maximum signal bandwidth of
0.8 × fDATA is always achieved.
Updating the Frequency Tuning Word
The frequency tuning word registers do not get updated
immediately upon writing as the other configuration registers
do. After loading the FTW registers with the desired values,
Bit 2 of Register 0x5A must transition from 0 to 1 for the new
FTW to take effect.
Phase Offset Adjustment
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9148s
are programmed for synchronization. The phase offset allows
for the adjustment of the output timing between the devices.
The static phase adjustment is sourced from the NCO Phase Offset
Word[15:0] value located in Register 0x58 and Register 0x59.



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