ATmega16U4 datasheet(155/408 Pages) ATMEL

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155

7766D–AVR–01/09

ATmega16U4/ATmega32U4

The N variable represents the number of steps in dual-slope operation. The value of N equals to

the TOP value.

The extreme values for the OCR4C Register represent special cases when generating a PWM

waveform output in the Phase and Frequency Correct PWM mode. If the OCR4C is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be continu-

ously high for non-inverted PWM mode. For inverted PWM the output will have the opposite

logic values.

The general I/O port function is overridden by the Output Compare value (OC4x / OC4x) from

the Dead Time Generator, if either of the COM4x1:0 bits are set and the Data Direction Register

bits for the OC4X and OC4X pins are set as an output. If the COM4x1:0 bits are cleared, the

actual value from the port register will be visible on the port pin. The configurations of the Output

Compare Pins are described in Table 15-4.

15.8.4

PWM6 Mode

The PWM6 Mode (PWM4A = 1, WGM41 = 1 and WGM40 = x) provide PWM waveform genera-

tion option e.g. for controlling Brushless DC (BLDC) motors. In the PWM6 Mode the OCR4A

from the Waveform Generator is used for generating all waveforms. The PWM6 Mode also pro-

vides an Output Compare Override Enable Register (OC4OE) that can be used with an instant

response for disabling or enabling the Output Compare pins. If the Output Compare Override

Enable bit is cleared, the actual value from the port register will be visible on the port pin.

The PWM6 Mode provides two counter operation modes, a single-slope operation and a dual-

slope operation. If the single-slope operation is selected (the WGM40 bit is set to 0), the counter

counts from BOTTOM to TOP (defined as OCR4C) then restart from BOTTOM like in Fast PWM

Mode. The PWM waveform is generated by setting (or clearing) the Waveform Output (OCW4A)

at the Compare Match between OCR4A and TCNT4, and clearing (or setting) the Waveform

Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The

Timer/Counter Overflow Flag (TOV4) is set each time the counter reaches the TOP and, if the

interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

Whereas, if the dual-slope operation is selected (the WGM40 bit is set to 1), the counter counts

repeatedly from BOTTOM to TOP (defined as OCR4C) and then from TOP to BOTTOM like in

Phase and Frequency Correct PWM Mode. The PWM waveform is generated by setting (or

clearing) the Waveform Output (OCW4A) at the Compare Match between OCR4A and TCNT4

when the counter increments, and clearing (or setting) the Waveform Output at the he Compare

Match between OCR4A and TCNT4 when the counter decrements. The Timer/Counter Overflow

Flag (TOV4) is set each time the counter reaches the BOTTOM and, if the interrupt is enabled,

the interrupt handler routine can be used for updating the compare value.

The timing diagram for the PWM6 Mode in single-slope operation (WGM41 = 0) when the

COM4A1:0 bits are set to “10” is shown in Figure 15-15. The counter is incremented until the

Table 15-4.

Output Compare pin configurations in Phase and Frequency Correct PWM Mode

COM4x1

COM4x0

OC4x Pin

Disconnected

01OC4x

OC4x

Disconnected

OC4x

Disconnected

OC4x

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