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ATmega16U4 bảng dữ liệu(PDF) 142 Page - ATMEL Corporation |
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ATmega16U4 bảng dữ liệu(HTML) 142 Page - ATMEL Corporation |
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142 / 408 page  142 7766D–AVR–01/09 ATmega16U4/ATmega32U4 Figure 15-2. Timer/Counter4 Synchronization Register Block Diagram. 15.2.5 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT4 for accessing Timer/Counter4 counter value and so on. The definitions in Table 15-1 are used extensively throughout the document. 8-BIT DATABUS OCR4A OCR4A_SI TCNT4_SO OCR4B OCR4B_SI OCR4C OCR4C_SI TCCR4A TCCR4A_SI TCCR4B TCCR4B_SI TCNT4 TCNT4_SI OCF4A OCF4A_SI OCF4B OCF4B_SI TOV4 TOV4_SI TOV4_SO OCF4B_SO OCF4A_SO TCNT4 S A S A PLLTM1:0 != '00' CK PCK (clk TMR ) IO-registers Input synchronization registers Timer/Counter4 Output synchronization registers SYNC MODE ASYNC MODE 1 CK Delay 1/2 CK Delay ~1/2 CK Delay 1 PCK Delay 1 PCK Delay ~1 CK Delay TCNT4 OCF4 OCF4B TOV4 1/2 CK Delay 1 CK Delay OCR4D OCR4D_SI TC4H TC4H_SI TCCR4C TCCR4C_SI TCCR4D OCF4D OCF4D_SI OCF4D_SO OCF4D TC4H_SO TC4H TCCR4D_SI Table 15-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0. MAX The counter reaches its MAXimum value when it becomes 0x3FF (decimal 1023). TOP The counter reaches the TOP value (stored in the OCR1C) when it becomes equal to the highest value in the count sequence. The TOP has a value 0x0FF as default after reset. |
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