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ATmega16U4 bảng dữ liệu(PDF) 137 Page - ATMEL Corporation |
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ATmega16U4 bảng dữ liệu(HTML) 137 Page - ATMEL Corporation |
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137 / 408 page  137 7766D–AVR–01/09 ATmega16U4/ATmega32U4 14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1 14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3 • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the ICFn Flag, located in TIFRn, is set. • Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnC Flag, located in TIFRn, is set. • Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnB Flag, located in TIFRn, is set. • Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnA Flag, located in TIFRn, is set. • Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the TOVn Flag, located in TIFRn, is set. 14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1 Bit 7654 32 1 0 – –ICIE1 –OCIE1 C OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 – –ICIE3 –OCIE3 C OCIE3B OCIE3A TOIE3 TIMSK3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0000 00 0 0 Bit 7654 32 1 0 – –ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0000 00 0 0 |
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