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ATmega16U4 bảng dữ liệu(PDF) 128 Page - ATMEL Corporation |
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ATmega16U4 bảng dữ liệu(HTML) 128 Page - ATMEL Corporation |
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128 / 408 page ![]() 128 7766D–AVR–01/09 ATmega16U4/ATmega32U4 Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8) 14.10 16-bit Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A – TCCR1A 14.10.2 Timer/Counter3 Control Register A – TCCR3A • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func- tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How- ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver. TOVn(FPWM) and ICF n(if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7 65 43 2 1 0 COM1A 1 COM1A 0 COM1B 1 COM1B 0 COM1C 1 COM1C 0 WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 2 1 0 COM3A 1 COM3A 0 COM3B 1 COM3B 0 COM3C 1 COM3C 0 WGM31 WGM30 TCCR3A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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