ATmega16U4 datasheet(108/408 Pages) ATMEL

108 / 408 page

108

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Figure 14-1. 16-bit Timer/Counter Block Diagram

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Note:

1. Refer to “Pinout ATmega16U4/ATmega32U4” on page 3, Table 10-3 on page 71, and Table

10-6 on page 74 for Timer/Counter1 and 3 and 3 pin placement and description.

2. Tn only refers to T1 since T3 input is not available on the ATmega16U4/ATmega32U4

product

14.1.1

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-

ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 109. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the

Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these

registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the clock select logic is referred to as the timer clock (clk

Tn).

ICFn (Int.Req.)

TOVn

(Int.Req.)

Clock Select

Timer/Counter

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

Waveform

Generation

OCnA

OCnB

OCnC

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

OCFnA

(Int.Req.)

OCFnB

(Int.Req.)

OCFnC

(Int.Req.)

TCCRnA

TCCRnB

TCCRnC

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

TCLK

OCRnC

OCRnB

OCRnA

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