56F8167 datasheet(148/182 Pages) FREESCALE

148 / 182 page

56F8367 Technical Data, Rev. 9

148

Freescale Semiconductor

Preliminary

Figure 10-4 External Clock Timing

10.6 Phase Locked Loop Timing

10.7 Crystal Oscillator Timing

Table 10-14 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.

fosc

8.4

MHz

PLL output frequency2 (fOUT)

2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in

the 56F8300 Peripheral User Manual.

fop

160

—

260

MHz

PLL stabilization time3 -40

° to +125°C

3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.

tplls

—1

Table 10-15 Crystal Oscillator Parameters

Characteristic

Symbol

Min

Typ

Max

Unit

Crystal Start-up time

TCS

Resonator Start-up time

TRS

0.1

0.18

Crystal ESR

RESR

——

120

ohms

Crystal Peak-to-Peak Jitter

—

250

Crystal Min-Max Period Variation

TPV

0.12

—

1.5

Resonator Peak-to-Peak Jitter

TRJ

——

300

Resonator Min-Max Period Variation

TRP

——

300

Bias Current, high-drive mode

IBIASH

—250

290

μA

Bias Current, low-drive mode

IBIASL

—80

110

μA

External

Clock

VIH

VIL

Note: The midpoint is VIL + (VIH – VIL)/2.

90%

50%

10%

90%

50%

10%

tPW

tfall

trise

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