56F8167 datasheet(99/182 Pages) FREESCALE

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56F8367 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

5.6.9.3

Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.9.4

SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.9.5

SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)—

Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.9.6

Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.9.7

Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

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