MB90F334APMC datasheet(48/72 Pages) FUJITSU

48 / 72 page

MB90330A Series

DS07-13734-7E

(5) UART0, UART1, UART2, UART3 I/O extended serial timing

(VCC

= AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Notes :

• Above rating is the case of CLK synchronous mode.

• CL is a load capacitance value on pins for testing.

• tCP : Refer to “ (1) Clock input timing”.

Parameter

Symbol

Pin name

Conditions

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCKx

Internal shift clock

mode output pin is :

= 80 pF + 1TTL

8 tCP

⎯

SCK

↓→SOT delay time

tSLOV

SCKx,

SOTx

− 80

+ 80

Valid SIN

→SCK↑

tIVSH

SCKx,

SINx

100

⎯

SCK

↑→valid SIN hold time

tSHIX

SCKx,

SINx

⎯

Serial clock H pulse width

tSHSL

SCKx, SINx

External shift clock

mode output pin is :

= 80 pF + 1TTL

4 tCP

⎯

Serial clock L pulse width

tSLSH

SCKx, SINx

4 tCP

⎯

SCK

↓→SOT delay time

tSLOV

SCKx,

SOTx

⎯

150

Valid SIN

→SCK↑

tIVSH

SCKx,

SINx

⎯

SCK

↑→valid SIN hold time

tSHIX

SCKx,

SINx

⎯

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