TMS320VC5421 datasheet(30/88 Pages) TI

30 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial port (McBSP) (continued)

XCERyz15

XCERyz14

XCERyz13

XCERyz12

XCERyz11

XCERyz10

XCERyz9

XCERyz8

RW,+0

765

43210

XCERyz7

XCERyz6

XCERyz5

XCERy4

XCERyz3

XCERyz2

XCERyz1

XCERyz0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2

Figure 12. Transmit Channel Enable Registers Bit Layout for Partitions A to H

Table 9. Transmit Channel Enable Registers for Partitions A to H

Bit

Name

Function

15–0

XCERyz(15:0)

Transmit Channel Enable Register

XCERyz

n =0

Disables transmit of

nth channel in partition y.

XCERyz

n =1

Enables transmit of

nth channel in partition y.

Note:

y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0

The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI) protocol.

Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by

the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to

operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP multichannel

operating frequency on the ’5421 is 9 MBps. Nonmultichannel operation is limited to 38 MBps.

direct memory access (DMA) controller

The ’5421 includes two 6-channel direct memory access (DMA) controllers for performing data transfers

independent of the CPU, one for each subsystem. The DMA controller controls accesses to off-chip

program/data/IO and internal data/program memory. The primary function of the ’5421 DMA controller is to

provide code overlays and manage data transfers between on-chip memory, the peripherals, and off-chip

memory.

In the background of CPU operation,the ’5421 DMA allows movement of data between internal and external

program/data memory, and internal peripherals, such as the McBSPs and the HPI. Each subsystem has its own

independent DMA with six programmable channels, which allows for six different contexts for DMA operation.

The HPI has a dedicated auxiliary DMA channel. Figure 13 illustrates the memory map accessible by the DMA.

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