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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TMS320VC5421 bảng dữ liệu(PDF) 40 Page - Texas Instruments |
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TMS320VC5421 bảng dữ liệu(HTML) 40 Page - Texas Instruments |
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40 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PLL clock programmable timer During the lockup period, the PLL should not be used to clock the ’5421. The PLLCOUNT programmable lock timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is achieved. The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided by 16. The resulting lockup delay can therefore be set from 0 to 255 × 16 CLKIN cycles. The lock timer is activated when the operating mode of the clock generator is switched from DIV to PLL. During the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer decrements to zero, the PLL begins clocking the ’5421. Accordingly, the value loaded into PLLCOUNT is chosen based on the following formula: PLLCOUNT + Lockup Time 16 T CLKIN where TCLKIN is the input reference clock period and lockup time is the required VCO lockup time, as shown in Table 17. Table 17. VCO Lockup Time CLKOUT FREQUENCY (MHz) LOCKUP TIME ( µs) 5 23 10 17 20 16 40 19 60 24 80 29 100 35 |
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