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TMS320VC5421 bảng dữ liệu(PDF) 42 Page - Texas Instruments |
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TMS320VC5421 bảng dữ liệu(HTML) 42 Page - Texas Instruments |
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42 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 19. Peripheral Memory-Mapped Registers for Each DSP Subsystem NAME ADDRESS DESCRIPTION NAME DEC HEX DESCRIPTION DRR20 32 20 McBSP 0 Data Receive Register 2 DRR10 33 21 McBSP 0 Data Receive Register 1 DXR20 34 22 McBSP 0 Data Transmit Register 2 DXR10 35 23 McBSP 0 Data Transmit Register 1 TIM 36 24 Timer Register PRD 37 25 Timer Period Register TCR 38 26 Timer Control Register — 39 27 Reserved SWWSR 40 28 Software Wait-State Register BSCR 41 29 Bank-Switching Control Register — 42 2A Reserved SWCR 43 2B Software Wait-State Control Register HPIC 44 2C HPI Control Register (HMODE=0 only) — 45–47 2D–2F Reserved DRR22 48 30 McBSP 2 Data Receive Register 2 DRR12 49 31 McBSP 2 Data Receive Register 1 DXR22 50 32 McBSP 2 Data Transmit Register 2 DXR12 51 33 McBSP 2 Data Transmit Register 1 SPSA2 52 34 McBSP 2 Subbank Address Register† SPSD2 53 35 McBSP 2 Subbank Data Register† — 54–55 36–37 Reserved SPSA0 56 38 McBSP 0 Subbank Address Register† SPSD0 57 39 McBSP 0 Subbank Data Register† — 58–59 3A–3B Reserved GPIO 60 3C General-Purpose I/O Register — 61 3D Reserved CSIDR 62 3E Chip Subsystem ID register — 63 3F Reserved DRR21 64 40 McBSP 1 Data Receive Register 2 DRR11 65 41 McBSP 1 Data Receive Register 1 DXR21 66 42 McBSP 1 Data Transmit Register 2 DXR11 67 43 McBSP 1 Data Transmit Register 1 — 68–71 44–47 Reserved SPSA1 72 48 McBSP 1 Subbank Address Register† SPSD1 73 49 McBSP 1 Subbank Data Register† — 74–83 4A–53 Reserved DMPREC 84 54 DMA Priority and Enable Control Register DMSA 85 55 DMA Subbank Address Register‡ DMSDI 86 56 DMA Subbank Data Register with Autoincrement‡ DMSDN 87 57 DMA Subbank Data Register‡ CLKMD 88 58 Clock Mode Register (CLKMD) — 89–95 59–5F Reserved † See Table 20 for a detailed description of the McBSP control registers and their subaddresses. ‡ See Table 21 for a detailed description of the DMA subbank addressed registers. memory-mapped registers (continued) |
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