TMS320VC5421 datasheet(65/88 Pages) TI

65 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

reset, BIO, interrupt, and XIO timings

timing requirements for reset, BIO, interrupt, and XIO [H = 0.5 tc(CO)] (see Figure 32, Figure 33,

and Figure 34)

MIN

MAX

UNIT

th(RS)

Hold time, RS after CLKOUT low

th(BIO)

Hold time, BIO after CLKOUT low

th(INT)

Hold time, INTn, NMI, after CLKOUT low†

th(XIO)

Hold time, XIO after CLKOUT low

tw(RSL)

Pulse duration, RS low‡§

4H+5

tw(BIO)A

Pulse duration, BIO low, asynchronous†

tw(INTH)A

Pulse duration, INTn, NMI high (asynchronous)†

tw(INTL)A

Pulse duration, INTn, NMI low (asynchronous)†

tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup†

tsu(RS)

Setup time, RS before CLKIN low§

tsu(BIO)

Setup time, BIO before CLKOUT low

tsu(INT)

Setup time, INTn, NMI, RS before CLKOUT low

tsu(XIO)

Setup time, XIO before CLKOUT low†

† The external interrupts (INT0–INT1, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is

corresponding to a three-CLKOUT sampling sequence.

‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50

µs to ensure

synchronization and lock-in of the PLL.

§ RS can cause a change in clock frequency, changing the value of H (see the software-programmable phase-locked loop (PLL) section).

BIO

CLKOUT

A_RS, B_RS,

INTn, NMI

CLKIN

th(BIO)

th(RS)

tsu(INT)

tw(BIO)A

tsu(BIO)

tw(RSL)

tsu(RS)

Figure 32. Reset and BIO Timings

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