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STOP AND WAIT MODES

7733 Group User’s Manual

11–15

11.4.1 State of clocks f2 to f512 in wait mode

The state of clocks f2 to f512 in the wait mode can be selected by the system clock stop bit at wait state

(bit 5 at address 6C16: Refer to Figure 11.2.2.). When supply of clocks f2 to f512 is stopped in the wait

mode, power consumption can further be lowered.

When supply of clocks f2 to f512 is stopped, internal peripheral devices which use clocks f2 to f512 stop

operating as in the stop mode. Furthermore, when pin P42/

φ1 functions as a clock φ1 output pin, this pin

outputs “L” level. (Refer to Table 11.4.2.)

When supply of clocks f2 to f512 is not stopped, both of the internal peripheral devices’ operation and clock

φ1 output do not stop. Note that, in the microprocessor mode, clock φ1 output stops when the signal output

disable selection bit = “1.”

In both cases, internal clock

φ stops, so that the CPU does not operate. Furthermore, because clock fc32

does not stop operating, the clock timer continues operating. (Refer to Table 11.4.3.)

11.4.2 Output levels of external bus and bus control signals in wait mode

In the memory expansion or microprocessor mode, the output levels of the external bus and bus control

signals in the wait mode can be set by software. By setting the standby state selection bit (bit 0 at address

6D16) to “1,” these output levels become levels set by software. Figure 11.4.1 shows an output level setting

example in the wait mode.

In the single-chip mode, do not set the standby state selection bit to “1.” (Fix this bit to “0.”)

11.4 Wait mode

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