7733 datasheet(299/940 Pages) RENESAS

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instruction is executed, the watchdog timer is connected as follows;

WATCHDOG TIMER

7733 Group User’s Manual

10-2

The watchdog timer is described below and functions as follows:

• Detects a program runaway.

• Measures a certain time from when oscillation starts at termination of the stop mode.

(Refer to chapter “11. STOP AND WAIT MODES.”)

10.1 Block description

Figure 10.1.1 shows the block diagram of the watchdog timer.

10.1 Block description

Fig. 10.1.1 Block diagram of watchdog timer

Watchdog timer

2Vcc

detection

circuit

Watchdog timer frequency

selection flag

f32

f512

Value

FFF16

is set.

Writing to the watchdog timer

STP instruction

Hold request

RESET

Watchdog timer

interrupt request

(Note 1)

Clocks f8, f32, f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

Notes 1: Only when the system clock selection bit (bit 3 at address 6C16) = “1” and the stop mode is

terminated by an interrupt request generated, the watchdog timer is connected to clock f 8.

Clock f16 is input when one of the following conditions is satisfied;

• The port-Xc selection bit = “0” and the main clock external input selection bit = “1”

• The system clock selection bit = “0” and the main clock external input selection bit = “1”

• The port-Xc selection bit = “1,” the system clock selection bit = “1” and the sub clock external input

selection bit = “1”

When the STP

•Connected to clock f32 when the system clock selection bit = “0”

•Connected to clock f8 when the system clock selection bit = “1”

(Note 2)

(Note 3)

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