7733 datasheet(236/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–33

Fig. 8.3.7 Transmit operation

____

Fig. 8.3.8 Example of transmit timing (when internal clock and CTS function are selected)

8.3 Clock synchronous serial I/O mode

CLKi pin’s clock

UARTi transmission buffer register

Transmit data

MSB

LSB

UARTi transmission register

This is applied when the CLK polarity selection bit = “0.”

When the CLK polarity selection bit = “1,” data is shifted at the rising edge of

the transfer clock of CLKi pin.

D0 D1 D2 D3 D4 D5 D6 D7

TCLK

CTSi

CLKi

TENDi

TxDi

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

Data is set in UARTi transmission buffer register.

Transmit enable bit

Transmission buffer

empty flag

Transfer clock

Stopped because CTSi pin’s level = “H”

UARTi transmission register

←UARTi transmission buffer register

The above timing diagram is applied when

the following conditions are satisfied:

• Internal clock is selected.

CTS

function is selected.

CLK polarity selection bit = “0.”

UARTi transmit interrupt

request bit

Cleared to “0” when an interrupt request is accepted; otherwise,

cleared by software.

Transmission register

empty flag

Stopped because transmit enable bit = “0”

TENDi: Next transmit conditions are checked when this signal level becomes “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from the external.)

Tc = TCLK = 2(n+1)/fi

fi: BRGi’s count source frequency (f2, f16, f64, or f512)

n: Value set to BRGi

•

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