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7733 bảng dữ liệu(PDF) 222 Page - Renesas Technology Corp

tên linh kiện 7733
Giải thích chi tiết về linh kiện  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SERIAL I/O
7733 Group User’s Manual
8–19
(1) Interrupt priority level selection bits (bits 2 to 0)
These bits are used to select the priority level of the UARTi transmission interrupt or UARTi reception
interrupt. When using the UARTi transmission/reception interrupt, select one of priority levels 1 to 7.
When a UARTi transmission/reception interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL) and the requested interrupt is enabled only when its priority level
is higher than the IPL. (Note that this is applied when the interrupt disable flag (I) = “0.”) When these
bits are set to “0002” (level 0), the UARTi transmission/reception interrupt is disabled.
(2) Interrupt request bit (bit 3)
The UARTi transmission interrupt request bit is set to “1” when data is transferred from the UARTi
transmission buffer register to the UARTi transmission register.
The UARTi reception interrupt request bit is set to “1” when data is transferred from the UARTi receive
register to the UARTi receive buffer register. Note that these bits do not change when an overrun error
occurs.
When each interrupt request is accepted, the corresponding interrupt request bit is automatically
cleared to “0.” Note that each bit can be set to “1” or cleared to “0” by software.
8.2 Block description



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