7733 datasheet(622/940 Pages) RENESAS

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7733 Group User’s Manual

21-74

APPENDIX

Interrupt

Suppose that there is a routine where a certain interrupt request should not be accepted. (The other

interrupt requests are acceptable.)

Although when the interrupt priority level selection bits for the above interrupt are set to “0002,” in

other words, when this interrupt is set to be disabled, this interrupt request is actually accepted

immediately after the change of the priority level. Why did this occur and what should I do about it?

Interrupt request is

accepted

in this interval

CLB #07H, XXXIC ; The interrupt priority level selection bits are set to “0002”

; or the interrupt request bit is set to “0.”

LDA A,DATA

; The first instruction of a routine where a certain

interrupt request should not be accepted

As for the change of the interrupt priority level, when the following are met, the microcomputer may

pretend to accept an interrupt request immediately after this interrupt is set to be disabled:

• The next instruction (in the above example, it is the LDA instruction) is already stored into a instruc-

tion queue buffer for the BIU.

• Conditions for accepting the instruction which should not be accepted are satisfied immediately

before the next instruction in the instruction queue buffer is executed.

When writing to the memory • I/O, the CPU transfers an address and data to the BIU. And then, the

CPU executes the next instruction in the instruction queue buffer while the BIU is writing the data into

the actual address. Interrupt priority level is determined at the start of each instruction.

In the above case, the CPU executes the next instruction before the BIU completes the change of

the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with

the execution of the next instruction, the interrupt priority level before the change is detected and

its interrupt request is accepted.

(1/2)

Previous instruction

is executed.

(Instruction is prefetched.)

CPU operation

BIU operation

Interrupt priority detection time

Sequence of execution

Interrupt priority level selection bits are set.

Change of interrupt priority levels

is completed

Interrupt request is accepted.

Interrupt request is generated.

CLB instruction

is executed.

LDA instruction

is executed.

Appendix 9. Q & A

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