7733 datasheet(604/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21–56

The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown

in the table is calculated for DPRL=0. The number of cycles in the addressing mode concerning the DPR when DPRL

≠0 must be

incremented by 1.

The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether

the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE=“H.”

Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator

2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments

by 1.

3. The number of cycles increments by 2 when branching.

4. The operation code on the upper row is used for branching in the range of –128 to +127, and the operation code on the

lower row is used for branching in the range of –32768 to +32767.

5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1.

The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done

is 12. i1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of

registers among DT and PG to be saved.

The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done

is 14. i1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i2=1 when DPR is to be

restored.

8. The number of cycles is the case when the number of bytes to be transferred is even.

When the number of bytes to be transferred is odd, the number is calculated as;

7 + (i/2) ! 7 + 4

Note that, (i/2) shows the integer part when i is divided by 2.

9. The number of cycles is the case when the number of bytes to be transferred is even.

When the number of bytes to be transferred is odd, the number is calculated as;

9 + (i/2) ! 7 + 5

Note that, (i/2) shows the integer part when i is divided by 2.

10. The number of cycles is the case in the 16-bit

÷ 8-bit operation. The number of cycles is incremented by 16 for 32-bit ÷ 16-

bit operation.

11. The number of cycles is the case in the 8-bit ! 8-bit operation. The number of cycles is incremented by 8 for 16-bit ! 16-

bit operation.

12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments

by 1.

13. When flag m is 0, the byte in the table is incremented by 1.

DPR

Type of register

Number of cycles

Type of register

Number of cycles

Appendix 6. Machine instructions

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