7733 datasheet(592/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21–44

ACC,C

←ACC+M+C

ACC

←ACC∧M

Symbol

Functions

Details

Adds the carry, the accumulator and the memory

contents.The result is entered into the accumulator. When

the D flag is “0,” binary additions is done, and when the

D flag is “1,” decimal addition is done.

Obtains the logical product of the contents of the accumu-

lator and the contents of the memory . The result is en-

tered into the accumulator.

Shifts the accumulator or the memory contents one bit to

the left. “0” is entered into bit 0 of the accumulator or the

memory. The contents of bit 15 ( bit 7 when the m flag is

“1”) of the accumulator or memory before shift is entered

into the C flag.

Tests the specified bit of the memory. Branches when all

the contents of the specified bit is “0.”

Tests the specified bit of the memory. Branches when all

the contents of the specified bit is “1.”

Branches when the contents of the C flag is “0.”

Branches when the contents of the C flag is “1.”

Branches when the contents of the Z flag is “1.”

Branches when the contents of the N flag is “1.”

Branches when the contents of the Z flag is “0.”

Branches when the contents of the N flag is “0.”

Jumps to the address indicated by the program counter

plus the offset value.

Executes software interruption.

Branches when the contents of the V flag is “0.”

Branches when the contents of the V flag is “1.”

Makes the contents of the specified bit in the memory “0.”

Makes the contents of the C flag “0.”

Makes the contents of the I flag “0.”

Specifies the bit position in the processor status register

by the bit pattern of the second byte in the instruction, and

sets “0” in that bit.

Makes the contents of the V flag “0.”

Compares the contents of the accumulator with the con-

tents of the memory.

Mb=0?

Mb=1?

C=0?

C=1?

Z=1?

N=1?

Z=0?

N=0?

←PC±offset

←PG+1

(when carry occurs)

←PG–1

(when borrow occurs)

←PC+2

M(S)

←PG

←S–1

M(S)

←PCH

←S–1

M(S)

←PCL

←S–1

M(S)

←PSH

←S–1

M(S)

←PSL

←S–1

←1

PCL

←ADL

PCH

←ADH

←0016

V=0?

V=1?

←0

Makes the contents of the m flag “0.”

←0

PSb

←0

ACC–M

IMP

IMM

DIR

DIR,b

DIR,X

DIR,Y

(DIR)

(DIR,X)

(DIR),Y

Addressing modes

AND

(Notes 1,2)

ADC

(Notes 1,2)

ASL

(Note 1)

BBC

(Notes 3,5)

BBS

(Notes 3,5)

BCC

(Note 3)

BCS

(Note 3)

BEQ

(Note 3)

BMI

(Note 3)

BNE

(Note 3)

BPL

(Note 3)

BRA

(Note 4)

BRK

BVC

(Note 3)

BVS

(Note 3)

CLB

(Note 5)

CLC

CLI

CLM

CLV

CMP

(Notes 1,2)

CLP

op n

2 61 72 71

3 42

10 3

2 21

31 82

3 42

16 72

m=0

← b15 ··· b0 ←0

m=1

← b7 ··· b0 ←0

# op n# op n# op n#

op n# op

# op

#n #

25 47 2

0A 2

00 15 2

14 8

18 2

Appendix 6. Machine instructions

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