7733 datasheet(455/940 Pages) RENESAS

455 / 940 page

APPLICATIONS

7733 Group User’s Manual

17–48

Note: Regardless of this setting, in the following cases, pin

outputs “L” level in the stop mode:

q When the signal output disable selection bit is set to “0” in the microprocessor mode

q When the clock

output selection bit is set to “1” in the memory expansion mode

STP

VREF connection selection bit

“1”

(bit 5 at address 1F16)

Pin VREF is disconnected from resistor ladder

network.

Stop mode is selected.

Interrupt request

occurs.

Port P0 register

“001111112”

(address 216)

Port P1 register

“000000002”

(address 316)

Port P2 register

“000000002”

(address 616)

Port P3 register

“000010112”

(address 716)

Levels of ports other than the above are fixed.

Signal output disable selection bit

“1”

(bit 6 at address 6C16)

I/O pins’ levels of external bus and bus control signals

in the stop mode are set.

(These levels can be set by the corresponding port

In this example, I/O pins for “L”-active signals are set to

“H” and the other pins are set to “L.”

Ports which correspond to I/O pins of external bus

and bus control signals: Output mode

(This setting is done in order to output a value set

to a port register in the stop mode)

’s state in the stop mode is set (Note).

In this example, “L” level output is set.

Pin E’s output level in the stop mode is set.

In this example, it is set to “L.”

Port P0 direction register

“FF16”

(address 416)

Port P1 direction register

“FF16”

(address 516)

Port P2 direction register

“FF16”

(address 816)

Port P3 direction register

“FF16”

(address 916)

Main routine

Port P4 register’s bit which corresponds to P42 pin

“0”

(bit 2 at address A16)

Port P4 direction register’s bit which corresponds to P42 pin

“1”

(bit 2 at address C16)

Standby state selection bit

“1”

(bit 0 at address 6D16)

Standby state selection bit: “1”

(In the stop mode, a value which is set to the

corresponding port register is output from an I/O

pin of the external bus or bus control signals.)

Fig. 17.4.3 Fixing I/O pins’ levels of external bus and bus control signals (Microprocessor mode)

17.4 Power saving

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