7733 datasheet(438/940 Pages) RENESAS

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APPLICATIONS

7733 Group User’s Manual

17–31

(2) Initial settings for related registers

17.2 Serial I/O

X: It may be “0” or “1.”

Clock synchronous serial I/O mode

UART0 transmit/receive mode register (address 30 16)

Internal clock is selected.

X0 0

0 1

Must be fixed to “0.”

CTS

/RTS function is disabled.

BRG0 count source: f2

UART0 transmit/receive control register 0 (address 34 16)

0X X 0 0

Pin TXD0’s output structure: CMOS output

Transmit data is output at the falling edge of the transfer clock.

MSB first

When the system clock (main clock) frequency = 16 MHz,

transfer rate = 2 MHz

UART0 baud rate register (BRG0) (address 31 16)

0116

Transmission is enabled.

UART0 transmit/receive control register 1 (address 35 16)

Reception is disabled.

XX 0 X 1

UART0 transmission interrupt control register (address 71 16)

UART0 transmission interrupt is disabled.

Pin CLKS1 is in the output mode when not transferring.

Port P8 direction register (address 14 16)

XX 1

Pin CLKS1 outputs “H” level when not transferring.

Port P8 register (address 12 16)

X XX 1

By this setting, pin CLKS 1 functions as port P8 0 and outputs “H” level when not transferring,

in other words, when no clock is output.

Pin CLKS0 do the processing of “output when not transferring.”

(“H” level is output.)

Fig. 17.2.8 Initial settings for related registers

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