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SH7721 bảng dữ liệu(PDF) 118 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 2
CPU
Rev. 3.00 Jan. 18, 2008 Page 56 of 1458
REJ09B0033-0300
2.5.2
CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3
Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation Formula
Register
direct
Rn
Effective address is register Rn.
(Operand is register Rn contents.)
Register
indirect
@Rn
Effective address is register Rn contents.
Rn
Rn
Rn
Register
indirect with
post-increment
@Rn+
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
1/2/4
+
Rn + 1/2/4
Rn
After instruction execution
Byte: Rn + 1
→ Rn
Word: Rn + 2
→ Rn
Longword: Rn + 4
→ Rn
Register
indirect with
pre-decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
1/2/4
-
Rn - 1/2/4
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Longword: Rn – 4
→ Rn
(Instruction executed with
Rn after calculation)



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