SH7721 datasheet(117/1524 Pages) RENESAS

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Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 55 of 1458

REJ09B0033-0300

(4)

T Bit

The result of a comparison is indicated by the T bit in the status register (SR), and a conditional

branch is performed according to whether the result is True or False. Processing speed has been

improved by keeping the number of instructions that modify the T bit to a minimum.

Example:

ADD

#1, R0

; The T bit cannot be modified by the

ADD

instruction

CMP/EQ

#0, R0

; The T bit is set to 1 if R0 is 0.

TARGET

; Branch to TARGET if the T bit is set

1 (R0=0).

(5)

Literal Constant

Byte literal constant is placed inside the instruction code as immediate data. Since the instruction

length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction

code, but in a table in memory. The table in memory is referenced with a MOV instruction using

PC-relative addressing mode with displacement.

Example:

MOV.W

@(disp, PC), R0

(6)

Absolute Addresses

When data is referenced by absolute address, the absolute address value is placed in a table in

memory beforehand as well as word or longword literal constant. Using the method whereby

immediate data is loaded when an instruction is executed, this value is transferred to a register and

the data is referenced using register indirect addressing mode.

(7)

16-Bit/32-Bit Displacement

When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a

table in memory beforehand. Using the method whereby word or longword immediate data is

loaded when an instruction is executed, this value is transferred to a register and the data is

referenced using indexed register indirect addressing mode.

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