SH7052 datasheet(274/919 Pages) RENESAS

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• Bit 5—Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A

input capture or compare-match. The flag is not set in PWM mode.

Bit 5: IMF4A

Description

[Clearing condition]

(Initial value)

When IMF4A is read while set to 1, then 0 is written to IMF4A

[Setting conditions]

• When the TCNT4 value is transferred to GR4A by an input capture signal

while GR4A is functioning as an input capture register

•••• When TCNT4 = GR4A while GR4A is functioning as an output compare

• Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or compare-

match.

Bit 4: OVF3

Description

[Clearing condition]

(Initial value)

When OVF3 is read while set to 1, then 0 is written to OVF3

[Setting condition]

When the TCNT3 value overflows (from H'FFFF to H'0000)

• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D

input capture or compare-match.

Bit 3: IMF3D

Description

[Clearing condition]

(Initial value)

When IMF3D is read while set to 1, then 0 is written to IMF3D

[Setting conditions]

• When the TCNT3 value is transferred to GR3D by an input capture signal

while GR3D is functioning as an input capture register. However, IMF3D

is not set by input capture with a channel 9 compare match as the trigger

•••• When TCNT3 = GR3D while GR3D is functioning as an output compare

•••• When TCNT3 = GR3D while GR3D is functioning as a synchronous

SH7052 bảng dữ liệu(PDF) 274 Page - Renesas Technology Corp