SH7052 datasheet(174/919 Pages) RENESAS

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• Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify

increment/decrement of the DMA transfer source address.

Bit 13: SM1

Bit 12: SM0

Description

Source address fixed

(Initial value)

Source address incremented (+1 during 8-bit transfer, +2

during 16-bit transfer, +4 during 32-bit transfer)

Source address decremented (–1 during 8-bit transfer, –2

during 16-bit transfer, –4 during 32-bit transfer)

Setting prohibited

When the transfer source is specified at an indirect address, specify in source address register 3

(SAR3) the actual storage address of the data to be transferred as the data storage address (indirect

address).

During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this

case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size

specified by TS1 and TS0.

• Bits 9 and 8—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify

increment/decrement of the DMA transfer source address.

Bit 9: DM1

Bit 8: DM0

Description

Destination address fixed

(Initial value)

Destination address incremented (+1 during 8-bit transfer, +2

during 16-bit transfer, +4 during 32-bit transfer)

Destination address decremented (–1 during 8-bit transfer, –2

during 16-bit transfer, –4 during 32-bit transfer)

Setting prohibited

• Bits 5 and 4—Transfer Size 1 and 0 (TS1, TS0): These bits specify the size of the data for

transfer.

Bit 5: TS1

Bit 4: TS0

Description

Specifies byte size (8 bits)

(Initial value)

Specifies word size (16 bits)

Specifies longword size (32 bits)

Setting prohibited

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