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SH7052 bảng dữ liệu(PDF) 129 Page - Renesas Technology Corp |
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SH7052 bảng dữ liệu(HTML) 129 Page - Renesas Technology Corp |
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129 / 919 page ![]() 103 UBAMRL: Bit: 15 14 13 12 11 10 9 8 UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH designates whether to mask any of the break address bits established in UBARH, and UBAMRL designates whether to mask any of the break address bits established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. • UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits designate whether to mask the corresponding break address 31 to 16 bits (UBA31 to UBA16) established in UBARH. • UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits designate whether to mask the corresponding break address 15 to 0 bits (UBA15 to UBA0) established in UBARL. Bit 15 to 0: UBMn Description 0 Break address UBAn is included in the break conditions (Initial value) 1 Break address UBAn is not included in the break conditions Note: n = 31 to 0 |
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