SH7052 datasheet(127/919 Pages) RENESAS

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101

7.1.3

The UBC has the six registers shown in table 7.1. Break conditions are established using these

registers.

Table 7.1

Name

Abbr.

R/W

Initial

Value

Address*

Access

Size

User break address register H

UBARH

R/W

H'0000

H'FFFFEC00

8, 16, 32

User break address register L

UBARL

R/W

H'0000

H'FFFFEC02

8, 16, 32

User break address mask register H

UBAMRH

R/W

H'0000

H'FFFFEC04

8, 16, 32

User break address mask register L

UBAMRL

R/W

H'0000

H'FFFFEC06

8, 16, 32

User break bus cycle register

UBBR

R/W

H'0000

H'FFFFEC08

8, 16, 32

User break control register

UBCR

R/W

H'0000

H'FFFFEC0A 8, 16, 32

Note: * In register access, three cycles are required for byte access and word access, and six

cycles for longword access.

7.2

7.2.1

User Break Address Register (UBAR)

UBARH:

Bit:

UBA31

UBA30

UBA29

UBA28

UBA27

UBA26

UBA25

UBA24

Initial value:

R/W:

R/W

Bit:

UBA23

UBA22

UBA21

UBA20

UBA19

UBA18

UBA17

UBA16

Initial value:

R/W:

R/W

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