SH7052 datasheet(824/919 Pages) RENESAS

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23.3.3

Hardware Standby Mode Timing

Figure 23.2 shows sample pin timings for hardware standby mode. A transition to hardware

standby mode is made by driving the

HSTBY pin low after driving the RES pin low. Hardware

standby mode is canceled by driving

HSTBY high, waiting for clock oscillation to stabilize, then

switching

RES from low to high.

Oscillator

RES

HSTBY

RES pulse

width tRESW

Oscillation

settling

time

Reset

exception

processing

Figure 23.2 Hardware Standby Mode Timing

23.4

Software Standby Mode

23.4.1

Transition to Software Standby Mode

To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then execute

the SLEEP instruction. The SH7052F/SH7053F/SH7054F switches from the program execution

state to software standby mode. In software standby mode, power consumption is greatly reduced

by halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register

contents and on-chip RAM data are held as long as the prescribed voltages are applied (when the

RAME bit in SYSCR is 0). The register contents of some on-chip peripheral modules are

initialized, but some are not (table 23.4). The I/O port state can be selected as held or high

impedance by the port high impedance bit (HIZ) in SBYCR. For other pin states, refer to

Appendix B Pin States.

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