SH7052 datasheet(822/919 Pages) RENESAS

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23.2.3

Module Standby Control Register (MSTCR)

Bit:

—

MSTOP3



MSTOP0

Initial value:

R/W:

R/W

The module standby control register (MSTCR) is an 8-bit readable/writable register that controls

the standby state of the AUD, and UBC on-chip modules.

MSTCR is initialized to H'01 by a power-on reset.

Note:

The method of writing to MSTCR is different from that of ordinary registers to prevent

inadvertent rewriting. See section 23.2.4, Notes on Register Access, for more information.

• Bits 7 to 4—Reserved: These bits always read 0. The write value should always be 0.

• Bit 3—Module Stop 3 (MSTOP3): Specifies halting of the clock supply to the AUD on-chip

peripheral module. Setting the MSTOP3 bit to 1 stops the clock supply to the AUD. To cancel

halting of the clock supply to the AUD, first set the AUD software reset bit (AUDSRST) in the

system control register (SYSCR) to the AUD reset state value. Use of the AUD will then be

enabled by clearing the AUD reset.

Bit 3: MSTOP3

Description

AUD operates

(Initial value)

Clock supply to AUD stopped

• Bits 2 and 1—Reserved: These bits always read 0. The write value should always be 0.

• Bit 0—Module Stop 0 (MSTOP0): Specifies halting of the clock supply stop to the UBC on-

chip peripheral module.

Clearing the MSTOP0 bit to 0 starts the clock supply to the UBC.

Stopping clock supply to the UBC will reset the internal state of the UBC including its

registers.

Bit 0: MSTOP0

Description

UBC operates

Clock supply to UBC stopped

(Initial value)

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