SH7052 datasheet(787/919 Pages) RENESAS

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Start

Programming end

Set SWE1 bit in FLMCR1

Wait: tSSWE

n = 1

m = 0

Subroutine call

See Note 6 for pulse width

Yes

Wait: tSPV

Wait: tSPVR

Write Pulse (tSP10)

Set PV1 bit in FLMCR1

Perform H'FF dummy-write to verify address

Read verify data

Write data = verify data?

≥ n?

Compute additional-programming data

Wait: tCSWE

m = 1

128 byte data verify

complete?

m = 0?

Increment

address

Programming failure

Wait: tCSWE

Clear SWE1 bit in FLMCR1

≥ 1000?

Successively write 128-byte data from

reprogram data area in RAM to flash memory

Write Pulse (tSP30 or tSP200)

Store 128 bytes program data in program

data area and reprogram data area

Transfer additional-programming data

to additional-programming data area

Compute reprogram data

Clear PV1 bit in FLMCR1

Wait: tCPV

Transfer reprogram data to reprogram data area

Successively write 128-byte data from additional-

programming data area in RAM to flash memory

← n + 1

Data writes must be performed

in the memory-erased state.

Do not write additional data to

an address to which data is

already written.

Figure 21.13 Program/Program-Verify Flowchart (1)

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