SH7052 datasheet(592/919 Pages) RENESAS

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Table 16.3

Analog Input Channels and A/D Data Registers

Analog Input Channel A/D Data Register

Analog Input Channel

A/D Data Register

AN0

ADDR0

AN8

ADDR8

AN1

ADDR1

AN9

ADDR9

AN2

ADDR2

AN10

ADDR10

AN3

ADDR3

AN11

ADDR11

AN4

ADDR4

AN12

ADDR12

AN5

ADDR5

AN13

ADDR13

AN6

ADDR6

AN14

ADDR14

AN7

ADDR7

AN15

ADDR15

16.2.2

A/D Control/Status Register 0 (ADCSR0)

A/D control/status register 0 (ADCSR0) is 8-bit readable/writable register whose function includes

selection of the A/D conversion mode for A/D0.

ADCSR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software

standby mode.

Bit:

ADF

ADIE

ADM1

ADM0

CH3

CH2

CH1

CH0

Initial value:

R/W:

R/(W)*

R/W

Note: * Only 0 can be written, to clear the flag.

• Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.

Bit 7:

ADF

Description

Indicates that A/D0 is performing A/D conversion, or is in the idle state

(Initial value)

[Clearing conditions]

• When ADF is read while set to 1, then 0 is written to ADF

•••• When the DMAC is activated by ADI0

Indicates that A/D0 has finished A/D conversion, and the digital value has been

transferred to ADDR

[Setting conditions]

• Single mode: When A/D conversion ends

• Scan mode: When all set A/D conversions end

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