SH7052 datasheet(480/919 Pages) RENESAS

480 / 919 page

454

• Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing

error in asynchronous mode.

Bit 4: FER

Description

Receiving is in progress or has ended normally

(Initial value)

Clearing the RE bit to 0 in the serial control register does not affect the FER bit,

which retains its previous value.

[Clearing conditions]

• Power-on reset, hardware standby mode, or software standby mode

• When 0 is written to FER after reading FER = 1

A receive framing error occurred

When the stop bit length is two bits, only the first bit is checked to see if it is a 1.

The second stop bit is not checked. When a framing error occurs, the SCI

transfers the receive data into RDR but does not set RDRF. Serial receiving

cannot continue while FER is set to 1. In synchronous mode, serial transmitting is

also disabled.

[Setting condition]

FER is set to 1 if the stop bit at the end of receive data is checked and found to

be 0

• Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to

a parity error in asynchronous mode.

Bit 3: PER

Description

Receiving is in progress or has ended normally

(Initial value)

Clearing the RE bit to 0 in the serial control register does not affect the PER bit,

which retains its previous value.

[Clearing conditions]

• Power-on reset, hardware standby mode, or software standby mode

• When 0 is written to PER after reading PER = 1

A receive parity error occurred

When a parity error occurs, the SCI transfers the receive data into RDR but does

not set RDRF. Serial receiving cannot continue while PER is set to 1.

[Setting condition]

PER is set to 1 if the number of 1s in receive data, including the parity bit, does

not match the even or odd parity setting of the parity mode bit (O/

E) in the serial

mode register (SMR)

SH7052 bảng dữ liệu(PDF) 480 Page - Renesas Technology Corp